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  Interrupt Service

Interrupts provide the key to fast response to external events occurring asynchronously in time. The speed with which an operating system such as AMX can respond to an interrupt is critical to its success in real-time applications.

From time to time, AMX must inhibit interrupts while it performs a critical, indivisible sequence of operations. AMX keeps such intervals very short. For instance, even while AMX is switching from one task to another, it is able to respond to interrupts. In this case, it is possible that, as a result of servicing the interrupt, AMX may actually be instructed to switch to a task of higher priority than the one which it otherwise would have picked.

When an interrupt occurs, most processors automatically vector to a user provided Interrupt Service Procedure. If the device procedure wishes to use any of the AMX services, it must notify the AMX Interrupt Supervisor that the interrupt has occurred. It is then free to use a subset of the AMX services which are applicable to interrupt servicing. These include triggering tasks for execution, sending messages to tasks, waking tasks and signalling events.

Once the device has been serviced and the source of the interrupt cleared, AMX is notified with a call to the Interrupt Supervisor. If, as a consequence of servicing the interrupt, a task of higher priority than the interrupted task is capable of execution, AMX will automatically initiate a task switch. If no higher priority task is ready to begin or resume execution, AMX returns to the interrupted task.

To improve interrupt response, AMX permits nesting of interrupts on processors that support this feature. As soon as the user Interrupt Service Procedure has dismissed the source of the interrupt, interrupts can be enabled to permit response to other external events.


Interrupt Control
Function Service
cjksivtrd Read interrupt vector or exception
cjksivtwr Write interrupt vector or exception
cjksivtx Exchange interrupt vector or exception
cjksitrap Install task trap handler
cj_kpclock AMX Clock Handler
   
Worst case interrupt latency times are provided on separate AMX data sheets for each target processor.


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