Table of Contents

	Introduction
	Processor Effects
	Memory Effects
	Cache Effects
	Code and Data Location Effects
	Compiler Effects
	Interrupt Latency

Introduction

The current release of KADAK's AMX^TM Multitasking Executive (RTOS) is the fifth in a long series spanning more than 20 years of development. With AMX coded in C and with the increasing use of RISC processors running at speeds over 100 MHz, kernel timing metrics have become increasingly difficult to define and measure.

KADAK has developed an extensive suite of timing tests to measure the performance of its AMX Multitasking Kernel. Several processor manufacturers have expressed their appreciation for KADAK's timing information which, good or bad, tells it like it is. Special thanks go to Daniel Mann, the prolific 29K author at Advanced Micro Devices, for his insight and helpful interpretation of some of the measurement results.

Measurements of interrupt latency and task switching times are always subject to interpretation. They are very dependent on the specific hardware platform (processor and memory system) on which they were made. They are also dependent on the C compiler used to create the AMX kernel and the application which makes the measurements.

This document provides an introduction to the timing issues which you will encounter using any RTOS. It discusses some of the factors which make timing measurement so difficult and helps to explain why instruction counts and cycle counts can rarely be used to measure execution times.

Much of the information in this document is derived from the AMX Timing Guide in the AMX Reference Manual. A copy of the AMX Timing Guide is available for downloading.