Processor Effects

Today's RISC and superscalar microprocessors use many techniques to boost instruction execution speeds. Internal instruction queues are used to allow instruction fetch and decode operations to proceed while previously decoded instructions are executing. Multiple execution units are often employed to permit simultaneous, parallel execution of instructions. Register scoreboarding may occur so that execution only stalls when a particular instruction needs a result from another incomplete instruction.

Branch prediction may be used to force the processor to assume a particular execution path which is the expected norm. A time penalty is then incurred only in the rare cases when the prediction is in error.

Processors may use multiple register sets or register windowing schemes to improve procedure parameter passing and to minimize the register preservation requirements of procedures.