Memory Effects

The processor's interface to memory is the single greatest impediment to full speed instruction execution. Unless instructions can be fetched from memory with zero delay, instruction execution will stall.

Various techniques are used to improve memory access. The most obvious is the use of high speed memory devices which are matched to the processor clock speed. Unfortunately, cost often precludes this preferred solution.

Most high performance processors provide an autonomous memory control unit capable of independent execution. High speed, multi-ported memory buffers may be used to allow burst transfers of small blocks of data to or from memory in anticipation of the processor's needs. In some cases, the block transfer size is configurable. The manner in which instructions straddle these block boundaries can directly affect performance. Minor shifts of code up or down in memory may noticeably affect execution time.

The processor can minimize the effects of slow data memory if instructions with no external memory references can be executed while previous memory accesses complete. However, this technique depends on judicious ordering of instructions to meet the memory access constraints, a requirement which cannot always be met. The instruction ordering burden falls on the assembly language programmer or on the high level language code generator.